The present invention relates to a semiconductor memory cell which comprises at least a first transistor for readout, a second transistor for switching and an MIS (Metal-Insulator-Semiconductor) type diode for retaining information and which does not require a so-called refresh operation for retaining information. Otherwise, it relates to a semiconductor memory cell which comprises at least a first transistor for readout, a second transistor for switching, a junction type transistor for current control and an MIS type diode for retaining information and which does not require a so-called refresh operation for retaining information.
As a high-density semiconductor memory cell, conventionally, there is used a dynamic semiconductor memory cell that is called a single-transistor semiconductor memory cell including one transistor and one capacitor as shown in FIG. 210A. In the above semiconductor memory cell, an electric charge stored in the capacitor is required to be large enough to generate a sufficiently large voltage change on a bit line. However, with a decrease in the planar dimensions of the semiconductor memory cell, the capacitor formed in a parallel planar shape decreases in size, which causes the following new problem. When information stored as an electric charge in the capacitor of the semiconductor memory cell is read out, the read-out information is buried in a noise. Or, since the stray capacitance of the bit line in the semiconductor memory cell increases from generation to generation, only a small voltage change is generated on the bit line. As means for solving the above problems, there has been proposed a dynamic semiconductor memory cell having a trench capacitor cell structure as shown in FIG. 210B or a stacked capacitor cell structure. Since, however, the fabrication-related technology has its own limits on the depth of the trench (or groove) or the height of the stack, the capacitance of the capacitor is also limited. For this reason, dynamic semiconductor memory cells having the above structures are said to encounter the above limits unless expensive new materials are introduced for the capacitor as far as the dimensions thereof beyond the deep sub-micron rule (low sub-micron rule) are concerned.
In the planar dimensions smaller than those of the deep sub-micron rule (low sub-micron rule), the transistor constituting the semiconductor memory cell also has problems of deterioration of the drain breakdown voltage and a punchthrough from a drain region to a source region. There is therefore a large risk that current leakage takes place even if the voltage applied to the semiconductor memory cell is still within a predetermined range. When a semiconductor memory cell is made smaller in size, therefore, it is difficult to normally operate the semiconductor memory cell having a conventional transistor structure.
For overcoming the above limit problems of the capacitor, the present Applicant has proposed a semiconductor memory cell comprising two transistors or two transistors physically merged into one unit, as is disclosed in Japanese Patent Application No. 246264/1993 (JP-A-7-99251) corresponding to U.S. Pat. No. 5,428,238. The following explanation is made by referring to Japanese Patent Application No. 246264/1993 (JP-A-7-99251). The semiconductor memory cell shown in FIGS. 15(A) and 15(B) of the above Japanese Patent Application comprises a first semi-conductive region SC.sub.1 of a first conductivity type formed in a surface region of a semiconductor substrate or formed on an insulating substrate, a first conductive region SC.sub.2 formed in a surface region of the first semi-conductive region SC.sub.1 so as to form a rectifier junction together with the first semi-conductive region SC.sub.1, a second semi-conductive region SC.sub.3 of a second conductivity type formed in a surface region of the first semi-conductive region SC.sub.1 and spaced from the first conductive region SC.sub.2, a second conductive region SC.sub.4 formed in a surface region of the second semi-conductive region SC.sub.3 so as to form a rectifier junction together with the second semi-conductive region SC.sub.3, and a conductive gate G formed on a barrier layer so as to bridge the first semi-conductive region SC.sub.1 and the second conductive region SC.sub.4 and so as to bridge the first conductive region SC.sub.2 and the second semi-conductive region SC.sub.3, the conductive gate G being connected to a first memory-cell-selecting line, the first conductive region SC.sub.2 being connected to a write-in information setting line, and the second conductive region SC.sub.4 being connected to a second memory-cell-selecting line.
The first semi-conductive region SC.sub.1 (functioning as a channel forming region Ch.sub.2), the first conductive region SC.sub.2 and the second semi-conductive region SC.sub.3 (functioning as source/drain regions) and the conductive gate G constitute a switching transistor TR.sub.2. On the other hand, the second semi-conductive region SC.sub.3 (functioning as a channel forming region Ch.sub.1), the first semi-conductive region SC.sub.1 and the second conductive region SC.sub.4 (functioning as source/drain regions) and the conductive gate G constitute an information storing transistor TR.sub.1.
When information is written in the above semiconductor memory cell, the switching transistor TR.sub.2 is brought into an on-state. As a result, the information is stored in the channel forming region Ch.sub.1 of the information storing transistor TR.sub.1 as a potential or as an electric charge. When the information is read out, the threshold voltage of the information storing transistor TR.sub.1 seen from the conductive gate G varies, depending upon the potential or the electric charge stored in the channel forming region Ch.sub.1 of the information storing transistor TR.sub.1. Therefore, when the information is read out, the storage state of the information storing transistor TR.sub.1 can be judged from the magnitude of a channel current (including a zero magnitude) by applying a properly selected potential to the conductive gate G. The information is read out by detecting the operation state of the information storing transistor TR.sub.1.
That is, when information is read out, the information storing transistor TR.sub.1 is brought into an on-state or an off-state, depending upon the information stored therein. Since the second conductive region SC.sub.4 is connected to the second line, a current which is large or small depending upon the stored information ("0" or "1") flows in the information storing transistor TR.sub.1. In this way, the information stored in the semiconductor memory cell can be read out through the information storing transistor TR.sub.1.
Further, the present Applicant in Japanese Patent Application No. 251646/1997 (JP-A-10-154757) has proposed a semiconductor memory cell comprising three transistors such as a transistor TR.sub.1 for readout, a transistor TR.sub.2 for switching and a junction type transistor TR.sub.3 for current control.
In the above semiconductor memory cell, information is stored in the second semi-conductive region SC.sub.3. However, the second semiconductor-conductive region SC.sub.3 is a floating region, so that the information disappears due to a leak current after a certain period of time. For retaining the information, therefore, there is required an refresh operation every constant period of time.